Generating Single- and Double-Pattern Tests for Multiple CMOS Fault Models in One ATPG Run

A novel test pattern generation method for multiple dc and ac faults is presented. The fault models considered include line stuck-at, bridging, transition, and transistor stuck-open faults. All faults are transformed into stuck-at faults with some constraints in the proposed two-timeframe circuit model such that all considered faults can be represented utilizing the user-defined fault model supported currently by most commercial ATPG tools. This makes it possible to generate a compact set of patterns for both dc and ac faults in one ATPG run without needing to modify the ATPG tool. Both launch-on-capture and launch-on-shift test methods are supported. The experimental results on ISCAS'89 and ITC'99 benchmark circuits show the effectiveness of the proposed method (PM) compared to earlier PMs.