Study on Impact of Parasitic Capacitance on Performance of Graded Channel Negative Capacitance SOI FET at High Temperature

This paper focuses on studying the impact of parasitic capacitance (C
_p
) on the performance of nanoscale graded channel (GC) negative capacitance (NC) silicon-on-insulator (SOI) FET at elevated temperatures. The device performance has been extensively explored for a range of C
_p
values for temperature range 300-400 K by employing simulation framework that uses TCAD models with Landau Khalatnikov equation. The advantages of GC design and NC phenomenon have been investigated for a wide temperature range and optimum values of C
_p
have been obtained to achieve substantial enhancement in key device parameters such as differential voltage amplification, subthreshold swing (below 60 mV/dec), transconductance, transconductance efficiency, output characteristics, and unity gain frequency.