Effect of Sub-10nm Fin-widths on the Analog Performance of FinFETs

This work experimentally investigates the effect of fin-width (W
_fin
) scaling in sub-10nm regime on the analog performance of nFinFETs. It is shown that the device trans-conductance (g
_m
) degrades and output conductance (g
_ds
) improves with reduction in W
_fin
. Various sources affecting the variability of gm and g
_ds
in sub-10nm W
_fin
regime are also explored. Through different analog performance metrics, it is shown that the analog performance of thinner fin FinFETs can be further increased by properly optimizing the S/D resistance and gate dielectric.