Micro-fabricated Surface Electrode Ion Trap with 3D-TSV Integration for Scalable Quantum Computing

In this paper, 3D architecture for TSV integrated Si surface ion-trap is proposed, in which the TSV and microbump technology is used to connect the surface electrodes of ion trap to a bottom Si interposer. The pseudopotential simulation is used to determine the trapped ion height for both the “planar trap” and “TSV trap” geometry. No significant deviation in the pseudopotential for both cases is observed. Preliminary micro-fabricated ion-trap chips are characterized. The proposed technology is promising in form factor and parasitic reduction of micro-fabricated surface ion-trap for scalable quantum computing application.