The Effects of Realistic U-shaped Source /Drain on DC/AC Performances of Silicon Nanosheet FETs for Sub 5-nm Node SoC Applications

DC/AC performances of sub 5-nm node silicon nanosheet field-effect transistors having realistic source/drain (S/D) shape were extensively analyzed according to S/D excess depth (TSD) using TCAD. Deeper T
_SD
improves RC delay, but consumed more power due to significantly increased leakage currents of parasitic bottom transistor. These results were more sensitive to T
_SD
in PFETs than in NFETs due to S/D dopant diffusion effect. Thus, more elaborate S/D process (recess, epitaxy and anneal) was required for PFETs than NFETs.