A Low-Jitter 10GHz PLL Based on Adaptive Bandwidth Technique for Muti-Rate Serial Link Data Transmitter

A wideband low-jitter phase-locked loop (PLL) presented in this paper adopts the adaptive-bandwidth technique and a two-stage ring oscillator which can be used for multi-rate serial link transmitter application. The two-stage ring oscillator is used to provide a high output frequency with optimal jitter performance, and the adaptive bandwidth technique is applied to guarantee the stability of the loop. The PLL was fabricated in a 28nm CMOS process, and the core occupies 0.05mm
²
. The experiment results show that the PLL has good robustness over PVT variation. The adaptive bandwidth PLL can generate clock with frequency from 6GHz to lOGHz. The measured Peak-Peak jitter at lOGHz is 10ps when the supply noise under the 1% of itself.