A 0.78mW Inductor-less 21GHZ CML frequency divider in 65nm CMOS

A high-speed frequency divider circuit used in the phase-locked loop of the RF transceiver is designed in 65nm CMOS process with a supply voltage of 1.3V. The designed frequency divider circuit improves and optimizes the traditional pseudo-differential structure to achieve a frequency division range of 0.5-21.5 GHz at an input signal peak of 400 mV, and passes all process corner and temperature simulations. A symmetrical structure is used on the layout of the circuit layout and the connection distance is reduced as much as possible. The layout size is only 23.5 um×17.3 um. When the power supply voltage is 1.3V, the operating current is 601.9 uA, and the DC power consumption is 0.78 mW.