Influence of Digital Delay on the Zero-Sequence Voltage Injection Neutral-Point Potential Balance Algorithm for Three-Level NPC Inverters and Its Compensation Method

Three-level neutral-point-clamped (NPC) inverters need to ensure the balance of the neutral-point (NP) potential during operation. The zero-sequence voltage injection balance algorithms based on the carrier-based pulse width modulation (CBPWM) have been proposed in many papers and proved to be effective in controlling the NP potential. In industrial applications, the algorithms are mostly implemented by digital controllers, which have inherent computation digital delay. However, there is little attention to how the digital delay influences the balance algorithms. In this paper, the influence of the digital delay on the zero-sequence voltage injection balance algorithm has been studied in detail. It is found that the digital delay causes a fluctuation of the NP potential. The frequency of the fluctuation is 1/6 control frequency, and the amplitude of the fluctuation is related to the control frequency, the modulation index, the output current, and the dc-side capacitance. Furthermore, in order to eliminate the NP potential fluctuation caused by the digital delay, a digital delay compensation method is proposed in this paper. The correctness of the theoretical analysis and the effectiveness of the compensation method have been verified by the simulation and experiment results.