Aging Investigation of Digital Circuit using In-Situ Monitor

Handling process, voltage, temperature and aging variations have become an important challenge for advanced technology nodes to guarantee good performance. It is important to capture PVTA variations very accurately, in that context in-situ monitor captures both local and global variations accurately as they are placed inside the design at the end of critical paths. This paper presents the experimental results and analysis of aging with the help of in-situ monitor across different dies. Critical path ranking and slack modification due to aging effect and different supply voltage are analyzed. Compensation of aging through body-bias applied on PMOS and NMOS is discussed.