New Insights on device level TDDB at GHz speed in advanced CMOS nodes

Reliability for advanced CMOS node is becoming very challenging. With technology scaling and the hardening of operating conditions requirements, Time Dependent Dielectric Breakdown (TDDB) on static stress (DC) may be insufficient to generate margin on lifetime assessment. In this paper, an original design and test setup are proposed, to deeply investigate TDDB at circuit operating frequencies. It is demonstrated that TDDB in the GHz range can be greatly improved, with respect to DC TDDB by a factor 16 and 85 for 28FDSOI PMOSFETs and NMOSFETs respectively. In fact, increasing frequency postpones breakdown event, lowers its hardness and extends its progressivity. Such a study has strong implications for logic circuit lifetime estimation.