Configurable 8T SRAM for Enbling in-Memory Computing

To cope with the memory wall of von-Neumann computing architecture, the in-memory-computing (IMC) architecture has been proposed. The IMC architecture embeds logic into the memory array to reduce the data transfer between the processor and memory. This paper proposes a configurable 8T SRAM which can provide the functions of ternary content address memory, left shift, and right shift in addition to the storage function. The method only needs to modify the peripheral circuitry of an 8 T SRAM. The Hspice simulator is used to verify configurable 8T SRAM using TSMC 0.18μm CMOS technology.