Embedded Silicon Fan‐Out (eSiFO®) Technology for Wafer‐Level System Integration

The demand for miniaturized package size, higher performance and integration density, lower power consumption, and lower manufacturing cost drives the development of various new packaging technologies. Fan‐out wafer‐level package (FO‐WLP) has become a key‐enabling technology for multichip and 3D system integration. As one type of FO‐WLP, embedded silicon fan‐out (eSiFO) technology, in which silicon instead of molding compound was used as the fan‐out area, was proposed in 2015. The main difference between eSiFO and the typical FO‐WLP is that there is no epoxy molding compound in eSiFO package. This chapter presents design rules for the eSiFO package. The application of eSiFO is similar to extended wafer‐level ball grid array, which can be used to package high performance application‐specific integrated circuit, mobile baseband modem/application processor engine, power management unit, RF transceiver, audio/video codec, sensors, and other multi‐chip and system‐in‐package modules.