Design of Radiation Hardened Inverter using CMOS Process

This paper presents design of Radiation Hardened Inverter using CMOS process. The technique which is used to harden the inverter is Radiation Hardened by design which is implemented in this paper. Inverter is designed basically for use in electronic circuits where Radiation environment is present. Proposed V
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negative based Inverter is designed in Cadence–Virtuoso Schematic editor and simulated in Cogenda TCAD software suit. In this design particles are incident on active area that is input node of the circuit. Single event upset caused by different particle with different energies are observed on Radiation Hardened Inverter. Analysis of recovery time and output voltage level is measured. A comparison is made between conventional Inverter and Radiation Hardened Inverter and it shows that logic level do not change in Radiation Hardened Inverter