Design and Simulation of High-Speed Parallel/Sequential Simplified DES Code Breaking Based on FPGA

High performance Field Programmable Gate Array (FPGA) devices have the capability of implementing parallel computing by building parallel Processing Elements (PEs) called virtual processors. One important reason is that FPGAs are special purpose devices. Hence, implementing any system based on these devices will give faster and more precise results than those given by using PCs, even if parallel processing approaches been applied by PCs. In this paper, two systems based on FPGA devices have been built for High Performance Computing (HPC). Code breaking for Simplified Data Encryption Standard (DES) algorithm was depended as case study. The first system consists of one FPGA device operated in a sequential way. One FPGA device contains one PE works in sequential fashion. This PE represents one simplified DES algorithm with two complete rounds. While the second system is a parallel one, also it consists of one FPGA device, but programmed to be implemented in parallel manner. The FPGA device contains 512 PEs operated in a parallel fashion. Each PE represents two completed rounds of simplified DES algorithm. In the second system, FPGA device works in much higher speed than the first one, because of that it works in parallel manner. Hence, reflecting great effect toward reducing the code breaking time and providing better results.