FPGA Implementation of Zero Frequency Filter

Epoch is the instant of significant excitation during the production of a speech signal. Due to time varying nature of the excitation source and the vocal tract system, accurate detection of epochs from the speech remains a challenging area of research. Over the years several algorithms have been proposed for the detection of epochs. Among different techniques proposed in the literature, the zero frequency filter (ZFF) approach provides better performance for clean and degraded speech. The filter design originally proposed in ZFF has an infinite impulse response (IIR) filter followed by two detrenders. Later, the IIR implementation is simplified to finite impulse response(FIR) realization. In this paper, we have designed the efficient architecture for IIR, FIR realization of ZFF and implemented these two realizations on field programmable gate array (FPGA).