Impact of Threshold Voltage Instability on Static and Switching Performance of GaN Devices with p-GaN Gate

The p-GaN gate technology has been adopted to realize enhancement-mode GaN devices. However, the blocking voltage can cause the threshold voltage to drift in p-GaN devices In this paper, the impact of the threshold voltage instability on the static and switching performance of the p-GaN device is studied. Specifically, a V
_th
measurement circuit is first designed which is able to characterize the threshold voltage after applying a minimum high voltage pulse of 2 μs. From the experimental result, an increase of more than 0.7 V in V
_th
is observed within several μs after blocking the high voltage. The static characteristics of the same device are compared before and after blocking the high voltage, and a reduced knee point in the output characteristic is observed at a low gate-to-source voltage. Due to the static characteristic variation, the switching performance of the device is also changed after stressed with the high drain-to-source voltage. Specifically, from the double pulse test result at 400 V/25 A with R
_g
=20 Ω, more than 20% increase of turn-on loss is recognized after blocking the high voltage for 30 minutes. The turn on loss difference is minimized when the gate resistance value is reduced to 0 Ω. For the turn-off loss, the impact of V
_th
's shift is negligible. Detailed analysis is also provided to explain the experimental result. It is concluded that higher gate drive voltage and lower gate resistance helps to minimize the threshold voltage instability's effect on the device's performance.