Pareto Design and Switching Frequencies for SiC MOSFETs Applied in an 11 kW Buck Converter for EV-Charging

Utilisation of SiC semiconductors' fast switching speeds and high switching frequencies as a consequent are often in discussion. But which switching frequency is really optimal in terms of converter volume, losses and costs? Based on the example of a buck converter, this question is investigated, and a tool for loss calculation and design is described in this paper. A Pareto optimization of the converter is performed where the switching frequency is one of several design parameters. The buck converter can be realized by multiple rails interleaved, and several switches can be placed in parallel. Considered converter modes are continuous conduction mode, that allows hard-switching, ZVS, and incomplete ZVS depending on the switching frequency. Based on Pareto optimizations, a design is selected, and a laboratory sample of 5.5 kW for application in an EV battery charger is built up. Efficiencies of 99.5 % are achieved with switching frequencies of around 100 kHz.