Design of Active SiC MOSFET Gate Driver for Crosstalk Suppression Considering Impedance Coordination between Gate Loop and Power Loop

In a phase leg configuration of SiC MOSFETs, the crosstalk threatens the reliable operation of the devices and introduces additional loss. State-of-the-art methods suppressing the crosstalk fails to consider the influence of the gate loop impedance. This paper points out that the gate loop impedance should be carefully designed in terms of the crosstalk elimination, especially for SiC MOSFET with fast switching speed and low threshold voltage. Firstly, an impedance model considering the parasitics of the gate loop is proposed. Then it is pointed out that the crosstalk voltage induced across the impedance of the gate source of the SiC MOSFET is related to the oscillation frequency of the drain source ring voltage, which is decided by the parasitics of the power loop. To effectively eliminate the crosstalk voltage, the gate loop impedance and power loop impedance should be designed coordinately. Finally, a parallel capacitor of the gate source terminal of SiC MOSFET is added during the turn off period and with proposal capacitance selection, the crosstalk voltage is effectively reduced. The proposed analysis and method are experimentally verified through a double pulse test platform.