Physical Insights into the Low Current ESD Failure of LDMOS-SCR and its Implication on Power Scalability

A unique low current ESD failure during snapback region, which otherwise survive high current stress, is reported in LDMOS-SCR device. The failure is universal to LDMOS-SCR devices designed as self-protected MOS switch and found to be specific to a window of current between trigger and holding state, which can only be captured using high resistance load-line in TLP system. This resulted in severe power scalability issues in LDMOS-SCRs. In this work, while using systematic experiments and 3D TCAD simulations, we have developed detailed physical insights into the unique low current ESD failure phenomenon in LDMOS-SCR devices.