Single-Event Upset Responses of Dual- and Triple-Well D Flip-Flop Designs in 7-nm Bulk FinFET Technology

Triple-well designs provide excellent noise isolation in mixed-signal circuits. But the presence of deep-n-well significantly affects Single-Event (SE) response of these circuits. Comparison of dual-well and triple-well designs for recent technologies have shown inconsistent results. This paper presents SE response of dual-well and triple-well flip-flop (FF) designs at the 7-nm bulk FinFET node. Results show dual-well designs have significantly superior SE performance compared to triple-well designs over a wide range of supply voltages and for different particles. TCAD simulations for different depths of p-well show that collected charge increases when the depth of p-well decreases. The shallow p-well in the deep-n-well design results in strong charge confinement leading to increased SE cross sections.