An Accurate Device-Level Simulation Method to Estimate Cross Sections of Single Event Upsets by Silicon Thickness in Raised Layer

An accurate device-level simulation method to estimate cross sections (CS) of single event upsets for a standard latch is proposed. CS from the proposed method is compared with experimental results by heavy ions on a fabricated chip in a 65 nm FDSOI. Silicon thickness below silicide is parameterized to make CS coincident between simulation and measurement results. Silicon thickness is highly correlated to soft-error tolerance. By increasing silicon thickness, simulation results becomes closer to the measurement results. Device simulation results show that the cross section is proportional to the silicon thickness in the raised layer below silicide.