Thin-Film FD-SOI BIMOS Topologies for ESD Protection

BIMOS devices - fabricated with the 28 nm thin-film high-k/metal gate FD-SOI CMOS technology - are demonstrated to be promising candidates for ESD protection. This manuscript discloses layouts of various BIMOS topologies in the thin-film. Among them, a 2D matrix of BIMOS is proposed. Those novel topologies were conceived, measured and compared at room temperature. DC, TLP and VF-TLP characterization data are provided and discussed for further optimization.