Customized High Performance and Energy Efficient Communication Networks for AI Chips

The convolutional and deep neural networks are prevalent machine learning algorithms for real-world applications. As the neural network needs large computations, many artificial intelligence (AI) chips are designed to accelerate the computation. AI chips have achieved better energy efficiency and high computational capacity in the neural network implementation. The communication network in AI chips influences the data transformation and hardware efficiency. The network-on-chip (NoC) is one feasible solution to meet the data communication requirements in AI chips. This paper introduces the communication network in AI chips and the strategy of mapping neural network to chips with the extensible hierarchical architecture. We also conclude the opportunities for communication optimization in the design of AI chips. In this paper, we propose our processor architecture and optimize the performance and energy of intra-communication in chips from three aspects: data reuse, topology, and router architecture. The experimental results show that our optimization can totally achieve
$25.31\times $
latency reduction and
$79.92\times $
energy less than the baseline. The results show that our design can reduce the latency by
$5.47\times $
and save communication energy by
$7.5\times $
when compared with the state-of-the-art design DaDianNao. When compared with another design Eyeriss, our design can reduce latency by
$7.57\times $
and save communication energy by
$3.03\times $
.