Frequency Estimation Improvement for Single-Phase Phase-Locked Loop Using Digital RST controller

A single-phase phase-locked loop (PLL) is popular for line frequency estimation. However, the line voltage may not be a pure sinusoidal waveform in practice, which causes high noise in the estimated frequency signal generated from the PLL. An increasing system order using a digital RST controller is presented to enhance high-frequency rejection. Consequently, the estimated frequency signal is significantly improved to be precise and smooth, even under a distorted line voltage. The proposed control strategy was verified by simulation results.