Hardware Implementation of AES with S-Box Using Composite-Field for WLAN Systems

The Advanced Encryption Standard (AES) algorithm is the best choice for security services in many applications, such as WLAN systems. This paper presents an AES hardware using composite-field by decomposing the complex Galois-field GF(2
⁸
) to the lower order field. Conventional designs are based on the Lookup table Sbox (LUT-Sbox)[1] to implement the S-box and InvS-box that cost much memory and area. Our proposed design using combinational logic is based on composite-field in finite fields GF(2
⁸
). The area cost is reduced because most of the functionalities are shared for both S-box and InvS-box, they are implemented on the same hardware. The proposed implementation occupies 4.1 kGEs and the maximum frequency is 180 MHz. Our implementation uses Verilog HDL on Virtex7 FPGA board.