Power Reduction in Domino Logic Using Clock Gating in 16nm CMOS Technology

In this paper, a new technique of power reduction in a cmos domino logic is proposed. The proposed technique uses clock gating as well as output hold circuitery. Clock is passed to the domino logic only during the active state of the circuit. During standby mode, clock is bypassed while the state of the circuit is retained. A 2:1 multiplexer is used for clock gating and for retaining the state of the circuit. Simulation results are being carried out in a 2-input nand gate, 2-input nor gate and 1-bit conventional full adder cell in 16nm cmos technology. The power of the proposed circuit is reduced to an average of 99.37 percent with respect to standard domino logic. Propagation delay is slightly increased to an average of 4.53 percent. Area of the proposed circuit increases to four transistors per domino module.