A Sample and Hold with Clock Booster for Improved Linearity

This manuscript presents a novel Sample and Hold circuit with improve linearity. Designing of a clock booster is an important attribute in the proposed bootstrap circuit. This Sample and Hold circuit is designed in the 45nm CMOS process which operates at 1.1V of supply voltage. The experimental outcomes show that the proposed Sample and Hold circuit consumes 14.51μ W and 3.559 μ W of power at 1.1V and 800mV of power supply voltage. The area of the proposed Sample and Hold circuit is 424.35 μm². This proposed Sample and Hold circuit is used in biomedical or sensor applications at front end design. The experimental outcomes show that the Sample and Hold circuit reaches the Effective Number of Bits (ENOB) greater than 11 bits, Spurious free Dynamic Range (SFDR) of 56dB and Signal to Noise Ratio (SNR) of 50dB for a 13 KHz input signal frequency through 200KS/s sampling rate.