VLSI Architectures for Jacobi Symbol Computation

Jacobi symbol calculation is one of the major computation steps for certain cryptographic algorithms. In this paper, we propose a bit-sliced VLSI architecture for the same, essentially tailored for FPGA implementations that exploits the fast carry chain fabric for realizing the circuit. The architecture was essentially conceived through appropriate configuration of the target FPGA specific primitives to achieve an optimized realization in terms of delay. Our implementation outperforms behaviorally modeled circuit having similar functionality using higher levels of design abstraction, with respect to speed.