A finite field processor employing dual parallel data path for high-speed/low-power RS-ECC applications

We suggest a finite field processor for a Reed-Solomon decoder which can be used for next generation DVDP/ROM, HD-DVD applications. The suggested processor implements Massey-Berlekamp's FSR synthesis algorithm which solves Newton's identity to find the coefficients of the error locator polynomial. By employing a SIMD-like dual parallel pipelined data path which exploited the characteristics of the required computation of the FSR algorithm, the suggested processor shows about twice as much throughput at the same clock frequency compared with a single pipelined data path. Furthermore, it was implemented as a programmable processor rather than a dedicated architecture to a specific error number and length of code word, it has flexibility and extensibility regardless of the number of correctable errors/erasures and the length of code word. The suggested processor shows high-speed capability up to 320 MHz if implemented using 0.35 /spl mu/m technology. This high-speed nature can also be traded for lower-power consumption unless the aim of the application is high-speed explicitly by reducing the clock rate.