A New Hardware Self-Organizing Map Architecture with High Expandability

This paper proposes a new scalable hardware SOM architecture in which neurons can easily be increased. Learning of SOM is made of two operations, i.e., winner search and vector update. In the proposed SOM, the winner search is distributed among all neurons. Owing to the distributed winner search circuit, the neuron is modularized and the architecture provides high expandability that makes it easier to increase the neurons. All neurons work in parallel including the winner search, and the proposed SOM processes a single input vector within a single clock cycle. The proposed SOM was implemented in a FPGA, and its performance was examined. Preliminary results of the experiment are presented in this paper.