A Switched Capacitor Digital Sinewave Mixer for Software-Defined Radio

This letter proposes a discrete-time mixer: the sampled RF input is multiplied by digital sinewave-LO samples. The multiplication is implemented by charge sharing between a unary weighted sampling capacitor and an output capacitor. Spurious responses as low as -56 dBc are achieved due to the good linearity and matching properties of capacitors. Four 5 GS/s time-interleaved samplers are implemented to cover the entire RF range from 0.1 to 4.9 GHz, while simultaneously providing 50 Ω impedance matching. Any radio channel narrower than 20 MHz in this RF range can be received at a fixed 20 GS/s sample rate. The worst case spurious response, caused by time-errors in the interleaving clock phases, is at -36 dBc (uncalibrated). Other measured parameters, of the 28 nm CMOS IC occupying an active area of 0.45 mm², over the RF band from 1.1 to 4.9 GHz are: NF = 14-16 dB (single-side band), IIP3 . +12 dBm, P1dB.