A Time-optimized Test-Solution Scheme for the Analysis of Permanent Faults on NoC Interconnects

While ensuring the desired reliability and yield of a network-on-chip (NoC), one must concern in tackling faults on the interconnects of the NoCs. This paper presents a novel test-solution that addresses the effects of manufacturing faults and evaluates their impact on network performance. We present, for the first time, a test strategy that can handle coexistent permanent faults occurring on interswitch and local channels. The strategy scales up seamlessly to large NoCs regardless of routing algorithms, topology, and channel width. Simulation results show the evaluation of the proposed strategy, and provide deep insights into the underlying mechanism that affects the performance metric in the presence of various faults under realistic traffic scenarios in the network.