Design and Fabrication of Ink-Jet Printed Logic Gates using SWCNT-FET for Flexible Circuit Applications

This paper reports the fabrication of flexible thin inkjet printed logic gates using single-walled carbon nanotube field effect transistors (SWCNT-FET). PMOS transistors were made with SWCNT and optimized for better performance in the logic gates. Fabrication of gated on flexible substrate was reported and design concerns were studied as a crucial factor in the optimization of PMOS gate logics. The circuits included Inverters, AND logic, and OR logic. The logic gate performance was compatible to the circuit simulation observed by transistor models. Propagation delay of the gates was low enough to perform up to 10 kHz of clock rate in the circuits. These new logic gates have applications in biomedical interfacing and wearable electronics.