Comparator Design and Calibration for Flash ADCs within Two-Step ADC Architectures

This paper describes a foreground offset calibration scheme for a 3-bit flash analog-to-digital converter (ADC), which is integrated as a coarse ADC within an 8-bit two-step time-interleaved (TI) hybrid ADC architecture. The calibration path emulates the ADC's normal operation to establish realistic loading and transient effects. Analog circuitry for input generation in the calibration path was designed to pass a specific reference for each comparator. A digital-to-analog converter (DAC) generates the calibration voltages. The presented design approach also addresses integration challenges within the hybrid ADC, such as kickback noise and common-mode variations. Simulation techniques were developed to assess the calibration effectiveness in the hybrid ADC system and to determine the standard deviations of the offsets. A prototype chip was fabricated in 130nm CMOS technology for experimental verification of the calibration method. Evaluations of operation with 6-bit resolution at 500MS/s and 10.28MHz input frequency demonstrate a measured ENOB of 5.24 bits after automatic calibration with 500MS/s and an ENOB of 4.93 bits using a 1GS/s clock.