A Single-Channel 18.5 GS/s 5-bit Flash ADC using a Body-Biased Comparator Architecture in 22nm FD-SOI

This paper presents a flash ADC architecture employing a comparator well-body biasing technique to eliminate the classical differential-difference amplifier (DDA) as well as the power-hungry reference ladder to enable significant power savings. DDAs require two differential pairs, one for the actual input signal and the other for the reference voltage whereas the proposed comparator technique merely uses a single differential pair for the input signal reducing the power consumption of the power-hungry preamplifier by approx. 50%. Furthermore, the flash ADC reference levels of the presented flash ADC, are generated by altering the input transistor threshold voltages. The adopted 22nm FD-SOI technology provides a threshold voltage tuning gain of approx. 85mV/V. Using a 3V capacitive charge-pump, a nominal full-scale range of 500 mV
_ppd
is achieved. This way, the proposed method also eliminates comparator kickback and therewith the low impedance requirement to guarantee settling of the reference ladder. The adopted technology provides a strong isolation from the gate to the back-gate of the input devices. The proposed techniques are adopted in a 5-bit 18.5 GS/s flash ADC. The track-and-hold along with the isolating front-end input buffer provides 28 GHz input bandwidth. The front-end buffer and SC charge pump operate from a 1.5V power supply while all other building blocks (comparator and clock tree) operate from a 0.9V power supply. The total power consumption is 140mW including clock buffers. The ADC achieves a SNDR and SFDR of 31dB and 43 dBc and 28.5dB and 40 dBc respectively at low and Nyquist input frequencies.