A 13-bit 180-MS/s SAR ADC with Efficient Capacitor-Mismatch Estimation and Dither Enhancement

A 13-bit SAR ADC with bridged capacitor array is implemented. In order to calibrate the weight error due to parasite and mismatch. A weight redundant structure and a one-by-one foreground weight estimate scheme is proposed. A dithering mode can improve the dynamic performance further. A prototype is fabricated in a 28nm CMOS technology. The measurement of the ADC with conversion rate of 180MS/s achieves an SFDR of 79.1dBc and an SNDR of 64.3dBc, with remarkable improvement after calibration and dither.