High Gain Operational Amplifiers in 22 nm CMOS

In this paper, a single-stage and a two-stage high gain operational amplifiers (op-amp) developed in a 22nm fully depleted silicon on insulator (FDSOI) CMOS process are presented. High gain is achieved through the integration of a modified high output-impedance current mirror. The operations of the modified current mirror are investigated. The two stage opamp is capable of rail-to-rail operation with 0.8V power supply while driving a 1 pF load. The single-stage op-amp is simulated to have 69 dB minimum DC gain, 29MHz unity-gain bandwidth, with a phase margin of 86°. Whereas, the two-stage op-amp is simulated to have 103 dB minimum DC gain, 50 MHz unity-gain bandwidth, 50° phase margin.