A Subthreshold 10T SRAM Cell with Enhanced Read and Write Operations

This paper presents a novel 10T static random access memory (SRAM) cell for ultra-low voltage operations. A built-in read assist scheme is proposed to eliminate the read disturb issue. It significantly improves the read stability. In addition, a data-aware write assist technique is also proposed to enhance the write ability of the SRAM cell. Simulations are performed in a 40-nm standard CMOS technology at a 0.4V supply voltage. The experimental results indicate that the proposed 10T SRAM cell exhibits the best write margin and large read static noise margin. When compared with the conventional 6T SRAM cell, it achieves 2.95× larger read static noise margin and 1.93× higher write margin.