Mismatch Compensation in ISFET Arrays using a Parasitic Programmable Gate

In this paper, we show a compensation method for mismatch in large-scale ISFET arrays which is caused by the presence of trapped charge at the sensor's floating gate. To facilitate ISFET calibration, the Programmable-Gate method is used. We improve on a previously proposed gradient descent algorithm by making an a priori estimate of the calibration step size thus allowing to reduce the number of iterations to one. This is enabled by an initial characterisation of the programmable gate capacitor in order to determine the effect of the calibration signal on the pixel's output. Measured results of both approaches are presented using a 64×200 ISFET array with a parasitic PG capacitor located vertically inside the pixel stack such that pixel area is not compromised. Additionally, results are shown for two chips which correspond to different trapped charge spreads with both algorithms reducing the standard deviation of the trapped charge by an average of 78% and 66% respectively.