Application of Ring-Amplifiers for Low-Power Wide-Bandwidth Digital Subsampling ADC-PLL

A digital subsampling ADC-PLL is simulated using Verilog-A models with ring-amplifier designed in a 65nm CMOS process. The ADC-PLL utilizes a ring-amplifier to relax the design requirements of the ADC. The ring-amplifier provides high open loop gain due to its multi-stage structure while dynamic biasing enables fast settling performance. In the proposed digital subsampling ADC-PLL, the ring-amplifier is operated at a reference frequency of 100MHz and utilizes programmable closed-loop gain from 1 to 100 reducing the quantization noise contribution of the 4-bit flash ADC. The ADC-PLL has an rms jitter of 57.5 fs when only quantization of the ADC and DCO are considered.