A −40-dBc Integrated-Phase-Noise 45-GHz Sub-Sampling PLL with 3.9-dBm Output and 2.1% DC-to-RF Efficiency

This paper presents a millimeter-wave (mmW) sub-sampling PLL in 40 nm CMOS. Sub-sampling PLL reduces the in-band phase noise due to the charge pump lower than the ordinary N
²
× when frequency is multiplied by N. Two sub-sampling phase detectors (SSPD) and charge pumps (SSCP) are employed to cancel mixing products due to sub-sampling around the VCO output tone and to enhance loop gain. The out-of-band phase noise, dictated by the VCO phase noise, is reduced by employing a VCO consisting of transmission-line resonators, large MOSFET switches, and inverse-class-F output matching. The proposed PLL, operating at 45 GHz, achieves −40-dBc integrated phase noise (0.1 kHz–40 MHz), 3.9-dBm output power, and 2.1% DC-to-RF efficiency.