Analysis of Bitwise and Samplewise Switched Passive Charge Sharing SAR ADCs

This paper presents the analysis of bitwise and samplewise switched passive charge sharing for successive approximation register (SAR) analog-to-digital conversion (ADC). Closed-form analytic expressions of ADC transfer functions are derived based on charge conservation and validated by behavioral and schematic simulations. This leads to two elegant results for SAR ADCs with bitwise switched reference charge reservoirs (BS-RCRs). First, a binary-weighted SAR ADC implemented with BS-RCRs is transformed into a subradix-2 ADC. Second, the reference error caused by finite reservoir capacitance appears in the form of bit weight error. This error can be corrected digitally or by selecting a sufficiently large bit reference capacitance to bit weight capacitance ratio
$\beta $
. However, the reference error with samplewise switched reference charge reservoir (SS-RCR) is input dependent. In addition, an equivalent-circuit model-based analysis method is introduced, which shows more circuit intuition why BS-RCRs have better linearity than SS-RCR. A case study of an 11-bit 100-MS/s SAR ADC in 65-nm CMOS is presented.