High-Performance Algorithm Adaptations and Hardware Architecture for HEVC Intra Encoders

High computational complexity and heavy data/timing dependency in high efficiency video coding (HEVC) hinder the throughput of video encoding. In order to address both design challenges, we present high-performance algorithm adaptations and high-throughput hardware architecture for the HEVC intra encoders. Particularly, the chroma intra prediction includes the derived luma mode, which greatly improves the worst-case video compression performance. Compared with the HM-15.0 reference software, the proposed algorithms reduce the computational workload by 22%, while the average BD-Rate and BD-PSNR for classes A-F and 4K are 2.79% and -0.13 dB, respectively. This BD-Rate is lower than existing designs in the literature with the same video resolution. The field-programmable gate array (FPGA) implementation of proposed design shows it operates at 120 MHz and supports 45 f/s of 1080P video sequences using 196K logic elements and 127-KB on-chip SRAM. The application-specified integrated circuit (ASIC) implementation of the proposed design in TSMC 90 nm technology shows that its clock frequency reaches 320 MHz with a hardware gate count of 2186K and power consumption of 290 mW, and it supports real-time encoding of 4K videos at 30 f/s.