Parameterizable FPGA Implementation of SHA-256 using Blockchain Concept

This paper concentrates on the Design of Parameterizable Implementation of SHA-256 algorithm in FPGA imparting Blockchain Concepts. SHA-256 is the key principle utilized in Blockchain architecture to impart security and privacy into a system. This one way hash function generates unique output for a given input ensuring data authenticity and non- repudiation. Blockchain technology is gaining popularity in the Internet world due to its property of decentralization. Through this implementation, main goal is to introduce this new technology into VLSI domain for securing hardware digital system designs and SOC's(System On Chip). The proposed methodology enables any bit length input message to get converted to fixed length message digest known as Hash. The design for the proposed architecture was simulated in Modelsim and synthesized in Xilinx Vivado Design Suite using Artix 7 FPGA.