Systolic Array Implementation of Mix Column and Inverse Mix Column of AES

This paper construes systolic array based architecture for the implementation of mix column and inverse mix column layers of AES block cipher algorithm. Mix column layer oriented processing units (PEs) that relies on Galois field operations drives the platform for the systolic arrays. Usage of systolic approach for mix column provides better through- put implementations. Inference of high throughput for systolic architecture were obtained on comparing FOM computed for the systolic architecture implementation against conventional hardware implementations.