VLSI Architectures for 8 Bit Data Comparators for Rank Ordering Image Applications

The main objective of the proposed work is to develop a new Data comparator which gives an economical solution for sorting / Rank ordering networks on the basis of speed, power, and area. The proposed work comprises a design of six different comparators for 8 -bit comparison. The performances of these six different comparators were targeted for XCV1000-4bg560 using Xilinx 7.1i compiler tool using VHDL. It was found that Carry select logic based data comparator requires less area and suitable for reduced area applications. The Conventional bit wise logic based data comparator operated with less delay. Hence this architecture can be used for high speed application. The Twos complement using binary to excess one data converter consumes less power. Hence a twos complement based implementation is suitable for low power implementations. The Different architecture for data comparators were applied on parallel and pipelined architecture of modified shear sorting. These three architectures were compared with other existing median finding architectures. It was found that the CSLA based parallel architecture, CBC based pipelined architecture and 2BEC based pipelined architecture were stand out in area, speed and power when compared with conventional median finding algorithms.