Device Designs and Analog Performance Analysis for Negative-Capacitance Vertical-Tunnel FET

In this work, the device design and analog performance of GaAsSb/InGaAs negative-capacitance vertical-tunnel FET (NCVT-FET) are analyzed compared with TFET. The optimized device design of NCVT-FET is proposed to maximize its vertical tunneling over the corner tunneling. Negative capacitance enhances vertical tunneling more significantly than corner tunneling due to the amplified vertical electric field. The impacts of source overlap length, tunnel layer, and N++ doping concentration have been investigated. The optimized NCVT-FET exhibits small I
_off
(10 pA/μm) and large I
_on
(405μA/μm) at V
_DD
=0.5V with 14mV/decade sub V
_t
swing over 4 decades of current were obtained. Moreover, the optimized NCVT-FET shows higher transconductance g
_m,max
(+92%), higher g
_m
/I
_DS
, and larger cutoff frequency f
_T,max
(+75%) compared to TFET.