A Non-Slicing 3-D Floorplan Representation for Monolithic 3-D IC Design

In this paper, we propose a non-slicing 3-D floorplan representation to design block-level monolithic 3-D ICs, The new 3-D floorplan representation applied to simulated annealing-based optimization achieves smaller volume, shorter wire length, and lower dynamic power consumption than the Sequence Triple, Sequence Quintuple, and Slicing Tree 3-D floorplanning representations.