A 273–301-GHz Amplifier With 21-dB Peak Gain in 65-nm Standard Bulk CMOS

This letter presents a world-first 300-GHz amplifier in 65-nm standard bulk CMOS (1P9M GP). The amplifier has gain from 273 to 301 GHz, and the peak gain is 21 dB at 298 GHz. The amplifier has 16-stage positive-feedback commonsource topology. The power consumption is 35.4 mW from a 1.2-V supply. Transistor (1 μm × 8 μm) layout is optimized for minimizing gate and channel resistance to increase gain corner frequency from 250 GHz (conventional design kit-based transistor measurement result) to 270 GHz, and fmax from around 300 GHz (design kit based) up to 317 GHz. Four transistor widths of 8, 10, 20, and 30 μm with the optimized layout are compared with the terms of f
_max
proving that the 8-μm width transistor has the highest f
_max
and hence used in the 300-GHz amplifier design. The dc-blocking capacitors are 10-fF finger-based design, which has lower loss than conventional MOM capacitors, since the fingers are formed on the top metal that is the thickest metal layer in the process.