Predictive yield modeling of VLSIC's

This paper presents a comprehensive methodology for predictive modeling of yield losses in modern VLSI technologies. The in-line defect detection and characterization methods are discussed and a new electrical characterization vehicle (CV) methodology is introduced. A complete chip level yield model that takes into account all the defect mechanisms (random and systematic) is presented. We show that extremely good prediction accuracy is achievable if the micro-level yield models are developed taking into account the available redundancy schemes, and the defect density and size distributions are properly extracted from the inline and CV data. Several examples of practical applications of this comprehensive yield methodology are also given.